Parallel computer organization and design (Record no. 10153)

MARC details
000 -LEADER
fixed length control field 02996cam a2200385 i 4500
001 - CONTROL NUMBER
control field 17209903
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20180814020002.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 120314s2012 enka 001 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2012010634
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780521886758
040 ## - CATALOGING SOURCE
Original cataloging agency DLC
Language of cataloging eng
Transcribing agency DLC
Description conventions rda
Modifying agency DLC
042 ## - AUTHENTICATION CODE
Authentication code pcc
050 00 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.5
Item number .D754 2012
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 005.275
Edition number 23
Item number DUB-P
084 ## - OTHER CLASSIFICATION NUMBER
Classification number COM059000
Source of number bisacsh
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Dubois, Michel,
Dates associated with a name 1953-
245 10 - TITLE STATEMENT
Title Parallel computer organization and design
Statement of responsibility, etc Michel Dubois, University of Southern California, USA, Murali Annavaram, University of Southern California, USA, Per Stenström, Chalmers University of Technology, Sweden.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc New York:
Name of publisher, distributor, etc Cambridge University Press,
Date of publication, distribution, etc ©2012.
300 ## - PHYSICAL DESCRIPTION
Extent xvii, 542 pages :
Other physical details illustrations ;
Dimensions 25 cm
500 ## - GENERAL NOTE
General note Includes index.
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note Machine generated contents note: 1. Introduction; 2. Impact of technology; 3. Processor microarchitecture; 4. Memory hierarchies; 5. Multiprocessor systems; 6. Interconnection networks; 7. Coherence, synchronization, and memory consistency; 8. Chip multiprocessors; 9. Quantitative evaluations.
520 ## - SUMMARY, ETC.
Summary, etc "Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software"--
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Parallel computers.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer organization.
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element COMPUTERS / Computer Engineering.
Source of heading or term bisacsh
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Annavaram, Murali.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Stenström, Per.
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Cover image
Uniform Resource Identifier <a href="http://assets.cambridge.org/97805218/86758/cover/9780521886758.jpg">http://assets.cambridge.org/97805218/86758/cover/9780521886758.jpg</a>
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Contributor biographical information
Uniform Resource Identifier <a href="http://www.loc.gov/catdir/enhancements/fy1210/2012010634-b.html">http://www.loc.gov/catdir/enhancements/fy1210/2012010634-b.html</a>
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Publisher description
Uniform Resource Identifier <a href="http://www.loc.gov/catdir/enhancements/fy1210/2012010634-d.html">http://www.loc.gov/catdir/enhancements/fy1210/2012010634-d.html</a>
856 41 - ELECTRONIC LOCATION AND ACCESS
Materials specified Table of contents only
Uniform Resource Identifier <a href="http://www.loc.gov/catdir/enhancements/fy1210/2012010634-t.html">http://www.loc.gov/catdir/enhancements/fy1210/2012010634-t.html</a>
906 ## - LOCAL DATA ELEMENT F, LDF (RLIN)
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942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Item type Books
Koha issues (borrowed), all copies 1
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection code Home library Current library Shelving location Date acquired Bill No. Bill Date Cost, normal purchase price PO No. PO Date Total Checkouts Total Renewals Full call number Barcode Date last seen Date last borrowed Cost, replacement price Price effective from Vendor/Supplier Koha item type
    Dewey Decimal Classification     Computer Science and Engineering IIITD IIITD Reference 11/07/2014 IN8024/14-15 2014-07-11 4768.32 IIITD/LIC/BS/2012/02/88 2014-06-05 1 2 REF 005.275 DUB-P 004484 13/09/2018 13/08/2018 £ 64.00 11/07/2014 Shankar's Book Agency Pvt. Ltd. Books
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