MARC details
| 000 -LEADER |
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| fixed length control field |
03161nam a22004337a 4500 |
| 001 - CONTROL NUMBER |
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| control field |
21683284 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IIITD |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20240220174602.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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| fixed length control field |
m |o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr ||||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
170628s2018 gw |||| o |||| 0|eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
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| LC control number |
2019749502 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783319594187 |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.1007/978-3-319-59418-7 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(DE-He213)978-3-319-59418-7 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
IIITD |
| Language of cataloging |
eng |
| Description conventions |
pn |
| -- |
rda |
| Transcribing agency |
DLC |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TJFC |
| Source |
thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.381 |
| Edition number |
23 |
| Item number |
MEH-A |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mehta, Ashok B. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
ASIC/SoC functional design verification : |
| Remainder of title |
a comprehensive guide to technologies and methodologies |
| Statement of responsibility, etc |
by Ashok B. Mehta. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
California : |
| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
©2018 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxxi, 328 p. : |
| Other physical details |
ill. col. ; |
| Dimensions |
24 cm. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Chapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Microprocessors. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Processor Architectures. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Print version: |
| Title |
ASIC/SOC functional design verification. |
| International Standard Book Number |
9783319594170 |
| Record control number |
(DLC) 2017941514 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9783319594170 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9783319594194 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9783319866208 |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
0 |
| b |
ibc |
| c |
origres |
| d |
u |
| e |
ncip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
