MARC details
| 000 -LEADER |
|---|
| fixed length control field |
03470nam a22003137a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
21335604 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
IIITD |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20240614020003.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
191213s2020 nyu b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2019056087 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781108494540 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7872.P38 |
| Item number |
R388 2020 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
23 |
| Item number |
RAZ-D |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Razavi, Behzad |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Design of CMOS phase-locked loops : |
| Remainder of title |
from circuit level to architecture level |
| Statement of responsibility, etc |
by Behzad Razavi |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
New York : |
| Name of publisher, distributor, etc |
Cambridge University Press, |
| Date of publication, distribution, etc |
©2020. |
| 263 ## - PROJECTED PUBLICATION DATE |
|---|
| Projected publication date |
2003 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xv, 492 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"A quick search on Google brings up nearly two dozen books on PLLs. So why another one? This book addresses the need for a text that methodically teaches modern CMOS PLLs for a wide range of applications. The objective is to teach the reader how to approach PLLs from transistor-level design to architecture development. Based on 25 years of teaching courses on the subject and the latest trends in industry, this book deals with oscillators, phase noise, analog phase-locked loops, digital phase-locked loops, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers. The objective is to reach a broad spectrum of readers while maintaining a cohesive flow. As with my past writings, I have implemented a multitude of pedagogical tools to help the reader learn efficiently-and experience the pleasure of learning. One principle that I uphold in writing is to start with the simplest possible arrangement, teach how it works and what shortcomings it has, and then add components to it to improve its performance. This approach allows the reader to see how a basic architecture evolves to a complex system. After laying the theoretical foundation for each topic, I present a step-by-step design flow and proceed to design the circuit. And not all design efforts are successful. The reader can clearly see how certain decisions lead to a dead end and how we revise these decisions to reach a new, more practical solution. This exploratory mentality not only makes the process of learning more exciting but also helps the reader see why each component is necessary, what criteria govern its choice, and what not to do. A unique aspect of this book is its extensive use of simulations to teach design and investigate agreement between theory and practice. For each design, I use the theoretical basis to choose certain parameters and predict the performance, and then I simulate the circuit. If the simulation results do not agree with the predictions, I delve into the details and determine why. Another unique aspect of this book is that it leverages concepts from one field (e.g., wireless technology) to another (e.g., wireline communications) by bringing the vast knowledge in these fields under one roof. A website for the book provides additional resources for readers and instructors, including Powerpoint slides and a solutions manual"-- |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Phase-locked loops |
| General subdivision |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Metal oxide semiconductors, Complementary |
| General subdivision |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Oscillators, Electric |
| General subdivision |
Design and construction. |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
| Koha issues (borrowed), all copies |
2 |
