Guide to Computer Processor Architecture (Record no. 185019)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04142nam a22006015i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-18023-1 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240423130109.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 230125s2023 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783031180231 |
| -- | 978-3-031-18023-1 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-3-031-18023-1 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7895.M5 |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.A73 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYF |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM011000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYF |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.22 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Goossens, Bernard. |
| Relator term | author. |
| Relator code | aut |
| -- | http://id.loc.gov/vocabulary/relators/aut |
| 245 10 - TITLE STATEMENT | |
| Title | Guide to Computer Processor Architecture |
| Medium | [electronic resource] : |
| Remainder of title | A RISC-V Approach, with High-Level Synthesis / |
| Statement of responsibility, etc | by Bernard Goossens. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2023. |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2023. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XXV, 439 p. 261 illus., 196 illus. in color. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Undergraduate Topics in Computer Science, |
| International Standard Serial Number | 2197-1781 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Part I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computers. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Microprogramming . |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Operating systems (Computers). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Software engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer Hardware. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Control Structures and Microprogramming. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Operating Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Software Engineering. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783031180224 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783031180248 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Undergraduate Topics in Computer Science, |
| -- | 2197-1781 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/978-3-031-18023-1">https://doi.org/10.1007/978-3-031-18023-1</a> |
| 912 ## - | |
| -- | ZDB-2-SCS |
| 912 ## - | |
| -- | ZDB-2-SXCS |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-CSE-Springer |
No items available.