Field-Programmable Logic and Applications (Record no. 189085)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 07929nam a22006375i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-540-44687-3 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240423132545.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 121227s2001 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783540446873 |
| -- | 978-3-540-44687-3 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/3-540-44687-7 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.S88 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYD |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM011000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UYD |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.2 |
| Edition number | 23 |
| 245 10 - TITLE STATEMENT | |
| Title | Field-Programmable Logic and Applications |
| Medium | [electronic resource] : |
| Remainder of title | 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / |
| Statement of responsibility, etc | edited by Gordon Brebner, Roger Woods. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2001. |
| 264 #1 - | |
| -- | Berlin, Heidelberg : |
| -- | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| -- | 2001. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XV, 665 p. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Computer Science, |
| International Standard Serial Number | 1611-3349 ; |
| Volume number/sequential designation | 2147 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Invited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits™ Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement andDetailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores.-Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware -- ASystem on Chip for Power Line Communications According to European Home Systems Specifications. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer systems. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Software engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer networks . |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-aided engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer System Implementation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Software Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer Communication Networks. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Brebner, Gordon. |
| Relator term | editor. |
| Relator code | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Woods, Roger. |
| Relator term | editor. |
| Relator code | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783540424994 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783662179215 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Lecture Notes in Computer Science, |
| -- | 1611-3349 ; |
| Volume number/sequential designation | 2147 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/3-540-44687-7">https://doi.org/10.1007/3-540-44687-7</a> |
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| -- | ZDB-2-SCS |
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| -- | ZDB-2-SXCS |
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| -- | ZDB-2-LNC |
| 912 ## - | |
| -- | ZDB-2-BAE |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-CSE-Springer |
No items available.