Course reserves for VLSI Design Flow

  1. Term: MNS24
  2. Department: ECE
  3. Course number: ECE513/ECE313
  4. Section: UG/PG (REST)
  5. Instructors:
    • Dr. Sneh Saurabh
Courses
Title Author Item type Location Collection Call number Copy number Status Date due Notes Link
Verilog HDL synthesis : Bhasker, J. Reference IIITD
Reference
Electronics and Communication Engineering REF 621.392 BHA-V Not for loan Reference
Application-specific integrated circuits Smith, Michael John Sebastian Books IIITD
General Stacks
Engineering and Allied Operation REF 621.39 SMI-A Not for loan Reference
Electronic design automation for IC implementation, circuit design, and process technology Lavagno, Luciano ..et.al. Books IIITD
Reference
Electronics and Communication Engineering REF 621.3815 LAV-E Not for loan Reference
Electronic design automation for IC system design, verification, and testing Lavagno, Luciano Books IIITD
Reference
Computer Science and Engineering REF 621.3815 LAV-E Checked out Not for loan 13/01/2025 Reference
Synthesis and optimization of digital circuits De Micheli, Giovanni. Books IIITD
General Stacks
Electronics and Communication Engineering 621.395 MIC-S Not for loan Reference Record URL
Introduction to VLSI design flow Saurabh, Sneh Books IIITD
Reference
Electronics and Communication Engineering REF 621.395 SAU-I Not for loan Reference
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