Architecture of Computing Systems - ARCS 2010 [electronic resource] : 23rd International Conference, Hannover, Germany, February 22-25, 2010, Proceedings /

Keynote -- HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors -- Processor Design -- How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT -- Complexity-Effective Rename Table Design for Rapid Speculation Recovery -- An Embedded GC Module with Support for Multiple Mutators and Weak References -- Embedded Systems -- A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems -- Autonomic Workload Management for Multi-core Processor Systems -- Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture -- Organic Computing and Self-organization -- The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments -- On Deadlocks and Fairness in Self-organizing Resource-Flow Systems -- Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems -- Processor Design and Transactional Memory -- MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance -- Exploiting Inactive Rename Slots for Detecting Soft Errors -- Efficient Transaction Nesting in Hardware Transactional Memory -- Energy Management in Distributed Environments and Ad-Hoc Grids -- Decentralized Energy-Management to Control Smart-Home Architectures -- EnergySaving Cluster Roll: Power Saving System for Clusters -- Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids -- Performance Modelling and Benchmarking -- Compiler-Directed Performance Model Construction for Parallel Programs -- A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces -- JetBench:An Open Source Real-time Multiprocessor Benchmark -- Accelerators and GPUs -- A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics -- Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model.