Normal view MARC view ISBD view

Power-and performance-aware on-chip interconnection architectures for many-core systems

By:

Contributor(s):

Material type: Text

TextPublication details: New Delhi : IIITD, ©April,2017Description: xvi, 135p. : ill. ; 29cmSubject(s):

DDC classification:

Online resources:

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode	Item holds
Thesis	IIITD Reference	Electronics and Communication Engineering	REF ECE 2017 (Browse shelf(Opens below))	Not for loan		TH0018

Total holds: 0

Previous		No cover image available		No cover image available	No cover image available	No cover image available	No cover image available	Next
Previous	REF 681.2 RAS-D Distributed sensor systems :	REF 681.2 SAW-C Course in mechanical measurements and instrumentation and control	REF 681.2 SHA-E Estimation with applications to tracking and navigation	REF ECE 2017 Power-and performance-aware on-chip interconnection architectures for many-core systems	REF ECE 2017 Design and analysis of password-based authentication systems	REF ECE 2017 Cognitive subcarrier sharing schemes for cooperative D2D communication frameworks	REF ECE 2017 Wavelet transform learning and applications	Next

Include bibliography

There are no comments on this title.

to post a comment.