Writing testbenches using system verilog
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- 0387292217
- 9788184892697
- 621.392 22 BER-W
- TK7885.7 .B48 2006
Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds |
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IIITD General Stacks | Electronics and Communication Engineering | 621.392 BER-W (Browse shelf(Opens below)) | Available | 002733 |
Total holds: 0
This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
Includes bibliographical references and index.
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