000			01944nam a22002657a 4500
003			IIITD
005			20241001124335.0
008			230606b xxu||||| |||| 00| 0 eng d
020			_a9781009200813
040			_aIIITD
082			_a621.395 _bSAU-I
100			_aSaurabh, Sneh
245			_aIntroduction to VLSI design flow _cby Sneh Saurabh
260			_aNew York : _bCambridge University Press, _c©2023
300			_axxiv, 689 p. _c24 cm.
500			_aThis book includes an index.
505			_tPart I. Overview of VLSI Design Flow: Chapter 1. Foundation _tChapter 2. Introduction to Integrated Circuits _tChapter 3. Pre-RTL Methodologies _tChapter 4. RTL to GDS Implementation Flow _tChapter 5. Verification Techniques _tChapter 6. Testing Techniques _tChapter 7. Post-GDS Processes _tPart II. Logic Design: Chapter 8. Modeling Hardware using Verilog _tChapter 9. Simulation-based Verification _tChapter 10. RTL Synthesis _tChapter 11. Formal Verification, Chapter 12. Logic Optimization _tChapter 13. Technology Library _tChapter 14. Static Timing Analysis _tChapter 15. Constraints _tChapter 16. Technology Mapping _tChapter 17. Timing-driven Optimizations _tChapter 18. Power Analysis _tChapter 19. Power-driven Optimizations _tPart III. Design for Testability (DFT): Chapter 20. Basics of DFT _tChapter 21. Scan Design _tChapter 22. Automatic Test Pattern Generation (ATPG) _tChapter 23. Built-in Self-test (BIST) _tPart IV. Physical Design: Chapter 24. Basic Concepts for Physical Design _tChapter 25. Chip Planning _tChapter 26. Placement _tChapter 27. Clock Tree Synthesis (CTS) _tChapter 28. Routing _tChapter 29. Physical Verification and Signoff _tChapter 30. Post-silicon Validation.
650			_aVLSI
650			_aIntegrated circuits
650			_aVery large scale integration
650			_aDesign and construction
650			_aMetal oxide semiconductors
650			_aComplementary
942			_2ddc _cBK _028
999			_c171351 _d171351