000			03161nam a22004337a 4500
001			21683284
003			IIITD
005			20240220174602.0
006			m |o d |
007			cr |||||||||||
008			170628s2018 gw |||| o |||| 0|eng
010			_a 2019749502
020			_a9783319594187
024	7		_a10.1007/978-3-319-59418-7 _2doi
035			_a(DE-He213)978-3-319-59418-7
040			_aIIITD _beng _epn _erda _cDLC
072		7	_aTEC008010 _2bisacsh
072		7	_aTJFC _2bicssc
072		7	_aTJFC _2thema
082	0	4	_a621.381 _223 _bMEH-A
100	1		_aMehta, Ashok B.
245	1	0	_aASIC/SoC functional design verification : _ba comprehensive guide to technologies and methodologies _cby Ashok B. Mehta.
260			_aCalifornia : _bSpringer, _c©2018
300			_axxxi, 328 p. : _bill. col. ; _c24 cm.
505	0		_aChapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
520			_aThis book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
650		0	_aElectronic circuits.
650		0	_aLogic design.
650		0	_aMicroprocessors.
650	1	4	_aCircuits and Systems.
650	2	4	_aLogic Design.
650	2	4	_aProcessor Architectures.
776	0	8	_iPrint version: _tASIC/SOC functional design verification. _z9783319594170 _w(DLC) 2017941514
776	0	8	_iPrinted edition: _z9783319594170
776	0	8	_iPrinted edition: _z9783319594194
776	0	8	_iPrinted edition: _z9783319866208
906			_a0 _bibc _corigres _du _encip _f20 _gy-gencatlg
942			_2ddc _cBK
999			_c172187 _d172187