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001			978-3-540-77560-7
003			DE-He213
005			20240423125727.0
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008			100301s2008 gw | s |||| 0|eng d
020			_a9783540775607 _9978-3-540-77560-7
024	7		_a10.1007/978-3-540-77560-7 _2doi
050		4	_aQA76.9.C62
072		7	_aUK _2bicssc
072		7	_aCOM036000 _2bisacsh
072		7	_aUK _2thema
082	0	4	_a004.01513 _223
245	1	0	_aHigh Performance Embedded Architectures and Compilers _h[electronic resource] : _bThird International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings / _cedited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer.
250			_a1st ed. 2008.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2008.
300			_aXIII, 400 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v4917
505	0		_aInvited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
650		0	_aComputer arithmetic and logic units.
650		0	_aCompilers (Computer programs).
650		0	_aComputer systems.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650		0	_aComputer input-output equipment.
650		0	_aLogic design.
650	1	4	_aArithmetic and Logic Structures.
650	2	4	_aCompilers and Interpreters.
650	2	4	_aComputer System Implementation.
650	2	4	_aProcessor Architectures.
650	2	4	_aInput/Output and Data Communications.
650	2	4	_aLogic Design.
700	1		_aStenström, Per. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aDubois, Michel. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aKatevenis, Manolis. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aGupta, Rajiv. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aUngerer, Theo. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
710	2		_aSpringerLink (Online service)
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783540775591
776	0	8	_iPrinted edition: _z9783540847083
830		0	_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v4917
856	4	0	_uhttps://doi.org/10.1007/978-3-540-77560-7
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912			_aZDB-2-SXCS
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