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020 _a9783319133386
_9978-3-319-13338-6
024 7 _a10.1007/978-3-319-13338-6
_2doi
050 4 _aQA76.758
072 7 _aUMZ
_2bicssc
072 7 _aCOM051230
_2bisacsh
072 7 _aUMZ
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082 0 4 _a005.1
_223
245 1 0 _aHardware and Software: Verification and Testing
_h[electronic resource] :
_b10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings /
_cedited by Eran Yahav.
250 _a1st ed. 2014.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2014.
300 _aXVI, 302 p. 78 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aProgramming and Software Engineering,
_x2945-9168 ;
_v8855
505 0 _aUsing Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures -- Enhancing Scenario Quality Using Quasi-Events -- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems -- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification -- Generating Modulo-2 Linear Invariants for Hardware Model Checking -- Suraq — A Controller Synthesis Tool Using Uninterpreted Functions -- Synthesizing Finite-State Protocols from Scenarios and Requirements -- Automatic Error Localization for Software Using Deductive Verification -- Generating JML Specifications from Alloy Expressions -- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems -- Handling TSO in Mechanized Linearizability Proofs -- Partial Quantifier Elimination -- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study -- A Framework to Synergize Partial Order Reduction with State Interpolation -- Reduction of Resolution Refutations and Interpolants via Subsumption -- Read, Write and Copy Dependencies for Symbolic Model Checking -- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams -- Formal Verification of Secure User Mode Device Execution with DMA -- Supervisory Control of Discrete-Event Systems via IC3 -- Partial-Order Reduction for Multi-core LTL Model Checking -- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution.
520 _aThis book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014. The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range of topics in the sub-fields of testing and verification applicable to software, hardware, and complex hybrid systems.
650 0 _aSoftware engineering.
650 0 _aComputer science.
650 0 _aCompilers (Computer programs).
650 0 _aArtificial intelligence.
650 0 _aMachine theory.
650 0 _aComputer networks .
650 1 4 _aSoftware Engineering.
650 2 4 _aComputer Science Logic and Foundations of Programming.
650 2 4 _aCompilers and Interpreters.
650 2 4 _aArtificial Intelligence.
650 2 4 _aFormal Languages and Automata Theory.
650 2 4 _aComputer Communication Networks.
700 1 _aYahav, Eran.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319133379
776 0 8 _iPrinted edition:
_z9783319133393
830 0 _aProgramming and Software Engineering,
_x2945-9168 ;
_v8855
856 4 0 _uhttps://doi.org/10.1007/978-3-319-13338-6
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cSPRINGER
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