000 05502nam a22006255i 4500
001 978-3-642-24568-8
003 DE-He213
005 20240423130144.0
007 cr nn 008mamaa
008 111114s2011 gw | s |||| 0|eng d
020 _a9783642245688
_9978-3-642-24568-8
024 7 _a10.1007/978-3-642-24568-8
_2doi
050 4 _aQA76.9.C62
072 7 _aUK
_2bicssc
072 7 _aCOM036000
_2bisacsh
072 7 _aUK
_2thema
082 0 4 _a004.01513
_223
245 1 0 _aTransactions on High-Performance Embedded Architectures and Compilers IV
_h[electronic resource] /
_cedited by Per Stenström.
250 _a1st ed. 2011.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2011.
300 _aXV, 430 p. 222 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v6760
505 0 _aA High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation – Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent’s Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration.
520 _aTransactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008.
650 0 _aComputer arithmetic and logic units.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aComputer input-output equipment.
650 0 _aLogic design.
650 0 _aComputer networks .
650 0 _aCompilers (Computer programs).
650 1 4 _aArithmetic and Logic Structures.
650 2 4 _aProcessor Architectures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aComputer Communication Networks.
650 2 4 _aCompilers and Interpreters.
700 1 _aStenström, Per.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783642245671
776 0 8 _iPrinted edition:
_z9783642245695
830 0 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v6760
856 4 0 _uhttps://doi.org/10.1007/978-3-642-24568-8
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cSPRINGER
999 _c185652
_d185652