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020 _a9783540398646
_9978-3-540-39864-6
024 7 _a10.1007/13479
_2doi
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072 7 _aUYD
_2bicssc
072 7 _aCOM011000
_2bisacsh
072 7 _aUYD
_2thema
082 0 4 _a004.2
_223
245 1 0 _aAdvances in Computer Systems Architecture
_h[electronic resource] :
_b8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings /
_cedited by Amos Omondi, Stanislav Sedukhin.
250 _a1st ed. 2003.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2003.
300 _aXIV, 410 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x1611-3349 ;
_v2823
505 0 _aHow Can the Earth Simulator Impact on Human Activities -- Toward Architecting and Designing Novel Computers -- Designing Ultra-large Instruction Issue Windows -- Multi-threaded Microprocessors – Evolution or Revolution -- The Development of System Software for Parallel Supercomputers -- Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA -- Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research -- Design and Implementation of Java Processors -- MOOSS: CPU Architecture with Memory Protection and Support for OOP -- Reducing Access Count to Register-Files through Operand Reuse -- SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator -- Towards an Asynchronous MIPS Processor -- On Implementing High Level Concurrency in Java -- Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures -- A Novel Architecture for Genomic Sequence Searching and Alignment -- A Reconfigurable Multi-threaded Architecture Model -- Reconfigurable Instruction-Level Parallel Processor Architecture -- Mapping Applications to a Coarse Grain Reconfigurable System -- Packing with Boundary Constraints for a Reconfigurable Operating System -- Arithmetic Circuits Combining Residue and Signed-Digit Representations -- A New On-the-fly Summation Algorithm -- State Reordering for Low Power Combinational Logic -- User-Level Management of Kernel Memory -- Variable Radix Page Table: A Page Table for Modern Architectures -- L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy -- Legba: Fast Hardware Support for Fine-Grained Protection -- Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem -- Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor -- Performance of the AchillesRouter -- Latency Improvement in Virtual Multicasting -- A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks.
520 _aThis conference marked the ?rst time that the Asia-Paci?c Computer Systems Architecture Conference was held outside Australasia (i. e. Australia and New Zealand), and was, we hope, the start of what will be a regular event. The conference started in 1992 as a workshop for computer architects in Australia and subsequently developed into a full-?edged conference covering Austra- sia. Two additional major changes led to the present conference. The ?rst was a change from “computer architecture” to “computer systems architecture”, a change that recognized the importance and close relationship to computer arc- tecture of certain levels of software (e. g. operating systems and compilers) and of other areas (e. g. computer networks). The second change, which re?ected the increasing number of papers being submitted from Asia, was the replacement of “Australasia” with “Asia-Paci?c”. This year’s event was therefore particularly signi?cant, in that it marked the beginning of a truly “Asia-Paci?c” conference. It is intended that in the future the conference venue will alternate between Asia and Australia/New Zealand and, although still small, we hope that in time the conference will develop into a major one that represents Asia to the same - tent as existing major computer-architecture conferences in North America and Europe represent those regions.
650 0 _aComputer systems.
650 0 _aLogic design.
650 0 _aComputer arithmetic and logic units.
650 0 _aComputer input-output equipment.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aComputer networks .
650 1 4 _aComputer System Implementation.
650 2 4 _aLogic Design.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aProcessor Architectures.
650 2 4 _aComputer Communication Networks.
700 1 _aOmondi, Amos.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aSedukhin, Stanislav.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540201229
776 0 8 _iPrinted edition:
_z9783662166864
830 0 _aLecture Notes in Computer Science,
_x1611-3349 ;
_v2823
856 4 0 _uhttps://doi.org/10.1007/13479
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912 _aZDB-2-SXCS
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