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020			_a9783540453529 _9978-3-540-45352-9
024	7		_a10.1007/3-540-45352-0 _2doi
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245	1	0	_aFormal Techniques in Real-Time and Fault-Tolerant Systems _h[electronic resource] : _b6th International Symposium, FTRTFT 2000 Pune, India, September 20-22, 2000 Proceedings / _cedited by Mathai Joseph.
250			_a1st ed. 2000.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2000.
300			_aX, 314 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aLecture Notes in Computer Science, _x1611-3349 ; _v1926
505	0		_aInvited Lectures -- Stability of Discrete Sampled Systems -- Issues in the Refinement of Distributed Programs -- Challenges in the Verification of Electronic Control Units -- Model Checking -- Scaling up Uppaal -- Decidable Model Checking of Probabilistic Hybrid Automata -- Fault Tolerance -- Invariant-Based Synthesis of Fault-Tolerant Systems -- Modeling Faults of Distributed, Reactive Systems -- Threshold and Bounded-Delay Voting in Critical Control Systems -- Automating the Addition of Fault-Tolerance -- Reliability Modelling of Time-Critical Distributed Systems -- Scheduling -- A Methodology for the Construction of Scheduled Systems -- A Dual Interpretation of “Standard Constraints” in Parametric Scheduling -- Validation -- Co-Simulation of Hybrid Systems: Signal-Simulink -- A System for Object Code Validation -- Refinement -- Real-Time Program Refinement Using Auxiliary Variables -- On Refinement and Temporal Annotations -- Generalizing Action Systems to Hybrid Systems -- Verification -- Compositional Verification of Synchronous Networks -- Modelling Coordinated Atomic Actions in Timed CSP -- Logic and Automata -- A Logical Characterisation of Event Recording Automata -- Using Cylindrical Algebraic Decomposition for the Analysis of Slope Parametric Hybrid Automata -- Probabilistic Neighbourhood Logic -- An On-the-Fly Tableau Construction for a Real-Time Temporal Logic -- Verifying Universal Properties of Parameterized Networks.
650		0	_aCompilers (Computer programs).
650		0	_aComputer systems.
650		0	_aComputer science.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650		0	_aComputers, Special purpose.
650		0	_aLogic design.
650	1	4	_aCompilers and Interpreters.
650	2	4	_aComputer System Implementation.
650	2	4	_aComputer Science Logic and Foundations of Programming.
650	2	4	_aProcessor Architectures.
650	2	4	_aSpecial Purpose and Application-Based Systems.
650	2	4	_aLogic Design.
700	1		_aJoseph, Mathai. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
710	2		_aSpringerLink (Online service)
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783540410553
776	0	8	_iPrinted edition: _z9783662172131
830		0	_aLecture Notes in Computer Science, _x1611-3349 ; _v1926
856	4	0	_uhttps://doi.org/10.1007/3-540-45352-0
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