000			01690cam a22003857a 4500
001			14189837
003			IIITD
005			20220625020002.0
008			051205s2006 nyua b 001 0 eng d
010			_a 2005938214
016	7		_a977544923 _2GyFmDB
020			_a0387292217
020			_a9788184892697
035			_a(CStRLIN)PASGA3145095-B
035			_a(PSt) (Sirsi) a3145095
040			_aOHX _cOHX _dNIC _dDLC
042			_alccopycat
050	0	0	_aTK7885.7 _b.B48 2006
082	0	0	_a621.392 _222 _bBER-W
100	1		_aBergeron, Janick.
245	1	0	_aWriting testbenches using system verilog _cby Janick Bergeron.
260			_aNew Delhi : _bSpringer, _cc2006.
300			_axxvi, 412 p. : _bill. ; _c25 cm.
500			_aThis book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
504			_aIncludes bibliographical references and index.
650		0	_aComputer hardware description languages.
650		0	_aIntegrated circuits _xVerification.
700	1		_aBergeron, Janick. _tWriting testbenches, functional verification of HDL models.
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0663/2005938214-d.html
856	4	1	_3Table of contents only _uhttp://www.loc.gov/catdir/enhancements/fy0814/2005938214-t.html
906			_a7 _bcbc _ccopycat _d2 _encip _f20 _gy-gencatlg
942			_2ddc _cBK _04
999			_c8492 _d8492