| 000 | 01313cam a2200301 a 4500 | ||
|---|---|---|---|
| 001 | 2617176 | ||
| 005 | 20220911020003.0 | ||
| 008 | 980819s1999 maua b 001 0 eng | ||
| 010 | _a 98042471 | ||
| 020 | _a0792383214 | ||
| 020 | _a9788181285867 | ||
| 040 |
_aDLC _cDLC _dDLC |
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| 050 | 0 | 0 |
_aTK7874.75 _b.M35 1999 |
| 082 | 0 | 0 |
_a621.395 _221 _bMAH-T |
| 100 | 1 |
_aMaheshwari, Naresh, _d1970- |
|
| 245 | 1 | 0 |
_aTiming analysis and optimization of sequential circuits _cNareah Maheshwari, Sachin S. Sapatnekar. |
| 260 |
_aBoston, Mass. : _bKluwer Academic Publishers, _cc1999. |
||
| 300 |
_axv, 190 p. : _bill. ; _c24 cm. |
||
| 504 | _aIncludes bibliographical references (p. [171]-188) and index. | ||
| 650 | 0 |
_aIntegrated circuits _xVery large scale integration _xComputer-aided design. |
|
| 650 | 0 |
_aTime-series analysis _xData processing. |
|
| 700 | 1 |
_aSapatnekar, Sachin S., _d1967- |
|
| 856 | 4 | 2 |
_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0820/98042471-d.html |
| 856 | 4 | 1 |
_3Table of contents only _uhttp://www.loc.gov/catdir/enhancements/fy0820/98042471-t.html |
| 906 |
_a7 _bcbc _corignew _d1 _eocip _f19 _gy-gencatlg |
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| 942 |
_2ddc _cBK _02 |
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| 999 |
_c8505 _d8505 |
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