000			03633cam a22003618a 4500
001			16453917
003			IIITD
005			20140925151240.0
008			100910s2011 flu b 001 0 eng
010			_a 2010036073
020			_a9781439837108
040			_aDLC _cDLC
042			_apcc
050	0	0	_aTK5105.546 _b.D476 2011
082	0	0	_a621.3815 _222 _bFLI-D
084			_aCOM011000 _aCOM059000 _2bisacsh
100			_aFlich, Jose.
245	0	0	_aDesigning network on-chip architectures in the nanoscale era _cJose Flich, Davide Bertozzi.
260			_aBoca Raton, FL : _bChapman & Hall/CRC, _c2011.
263			_a1012
300			_axxxviii 490p.
490	0		_aChapman & Hall/CRC computational science
504			_aIncludes bibliographical references and index.
520			_a"Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"--
520			_a"Chip Multiprocessors (CMPs) are diving very aggressively into the marketplace since past efforts to speed up processor architectures in ways that do not modify the basic von Neumann computing model have encountered hard limits. The power consumption of the chip becomes the limiting factor and sets the rules for future CMP systems. As a result, the microprocessor industry is today leading the development of multicore and many-core architectures where, as the number of cores increases, efficient communication among them and with off-chip resources becomes key to achieve the intended performance scalability. This trend has helped overcome the skepticism of some system architects to embrace on-chip interconnection networks as a key enabler for effective system integration. Networks-on-chip (NoCs) make performance scalability more a matter of instantiation and connectivity rather than increasing complexity of specific architecture building blocks. This book comes as a timely and welcome addition to the wide spectrum of available NoC literature, as it has been designed with the purpose of describing in a coherent and well-grounded fashion the foundation of NoC technology, above and beyond a simple overview of research ideas and/or design experiences. It covers in depth architectural and implementation concepts and gives clear guidelines on how to design the key network component, providing strong guidance in a research field that is starting to stabilize, bringing "sense and simplicity" and teaching hard lessons from the design trenches. The book also covers upcoming research and development trends, such as vertical integration and variation tolerant design. It is a much needed "how-to" guide and an ideal stepping stone for the next ten years of NoC evolution"--
650		0	_aNetworks on a chip.
650		7	_aCOMPUTERS / Systems Architecture / General _2bisacsh.
650		7	_aCOMPUTERS / Computer Engineering _2bisacsh.
700	1		_aBertozzi, Davide.
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
942			_2ddc _cBK
999			_c8566 _d8566