MARC details
| 000 -LEADER |
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| fixed length control field |
01922nam a22002417a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IIITD |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20240830101807.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
240826b |||||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780521859721 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
IIITD |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.381 |
| Item number |
PRA-P |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
Practical design verification |
| Statement of responsibility, etc |
edited by Dhiraj K. Pradhan and Ian G. Harris |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
New York : |
| Name of publisher, distributor, etc |
Cambridge University Press, |
| Date of publication, distribution, etc |
©2009 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xi, 276 p. : |
| Other physical details |
ill. ; |
| Dimensions |
26 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Title |
1. Model checking and equivalence checking |
| -- |
2. Transaction-level system modeling |
| -- |
3. Response checkers, monitors, and assertions |
| -- |
4. System debugging strategies |
| -- |
5. Test generation and coverage metrics |
| -- |
6. SystemVerilog and Vera in a verification flow |
| -- |
7. Decision diagrams for verification |
| -- |
8. Boolean satisfiability and EDA applications |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Technology & Engineering -- Electronics -- Circuits -- Integrated. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Pradhan, Dhiraj K. |
| Relator term |
editor |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Harris, Ian G. |
| Relator term |
editor |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
