MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01450fam a2200289 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
1671323 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20180301020002.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
941007s1995 maua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
94041225 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9788173191008 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)31374251 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)ocm31374251 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(NNC)1671323 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
DLC |
| -- |
OrLoB |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.A73 |
| Item number |
F58 1995 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.22 |
| Edition number |
20 |
| Item number |
FLY-C |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Flynn, Michael J. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Computer architecture : |
| Remainder of title |
pipelined and parallel processor design |
| Statement of responsibility, etc |
Michael J. Flynn. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
New Delhi : |
| Name of publisher, distributor, etc |
Narosa, |
| Date of publication, distribution, etc |
c1995. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xix, 788 p. : |
| Other physical details |
ill. ; |
| Dimensions |
26 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
1. |
| Title |
Architecture and Machines -- |
| Miscellaneous information |
2. |
| Title |
Time, Area, and Instruction Sets -- |
| Miscellaneous information |
3. |
| Title |
Data: How Programs Behave -- |
| Miscellaneous information |
4. |
| Title |
Pipelined Processor Design -- |
| Miscellaneous information |
5. |
| Title |
Cache Memory -- |
| Miscellaneous information |
6. |
| Title |
Memory System Design -- |
| Miscellaneous information |
7. |
| Title |
Concurrent Processors -- |
| Miscellaneous information |
8. |
| Title |
Shared Memory Multiprocessors -- |
| Miscellaneous information |
9. |
| Title |
I/O and the Storage Hierarchy -- |
| Miscellaneous information |
10. |
| Title |
Processor Studies -- |
| -- |
Appendix A DTMR Cache Miss Rates -- |
| -- |
Appendix B SPECmark vs. DTMR Cache Performance -- |
| -- |
Appendix C Modeling System Effects in Caches -- |
| -- |
Appendix D New DRAM Technologies -- |
| -- |
Appendix E M/G/1 Queues -- |
| -- |
Appendix F Some Details on Bus-Based Protocols. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Microprocessors |
| General subdivision |
Design and construction. |
| 900 ## - EQUIVALENCE OR CROSS-REFERENCE-PERSONAL NAME [LOCAL, CANADA] |
|---|
| Numeration |
TOC |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Item type |
Books |
| Koha issues (borrowed), all copies |
1 |
