Writing testbenches using system verilog

By:

Bergeron, Janick

Contributor(s):

Bergeron, Janick. Writing testbenches, functional verification of HDL models

Material type: Text

TextPublication details: New Delhi : Springer, c2006.Description: xxvi, 412 p. : ill. ; 25 cmISBN:

0387292217
9788184892697

Subject(s):

DDC classification:

621.392 22 BER-W

LOC classification:

TK7885.7 .B48 2006

Online resources:

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Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode	Item holds
Books	IIITD General Stacks	Electronics and Communication Engineering	621.392 BER-W (Browse shelf(Opens below))	Available		002733

Total holds: 0

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Previous	621.3916 DAV-M MSP430 microcontroller basics	621.3916 RAY-A Advanced microprocessors and peripherals	621.392 ASH-S The student's guide to VHDL	621.392 BER-W Writing testbenches using system verilog	621.392 BHA-V A VHDL primer	621.392 BHA-V A VHDL primer	621.392 BHA-V A VHDL primer	Next

This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.

Includes bibliographical references and index.

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